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? semiconductor components industries, llc, 2011 december, 2011 ? rev. p0 1 publication order number: NCN49597/d NCN49597 product preview power line carrier modem on semiconductor?s NCN49597 is an iec 61334 ? 5 ? 1 compliant power line carrier modem using spread ? fsk (s ? fsk) modulation for robust low data rate communication over power lines. NCN49597 is built around an arm processor core, and includes the mac layer. with this robust modulation technique, signals on the power lines can pass long distances. the half ? duplex operation is automatically synchronized to the mains, and can be up to 4800 bits/sec. the product configuration is done via its serial interface, which allows the user to concentrate on the development of the application. the NCN49597 is implemented in on semiconductor mixed signal technology, combining both analog circuitry and digital functionality on the same ic. features ? power line carrier modem for 50 and 60 hz mains ? fully compliant to iec 61334 ? 5 ? 1 and cenelec en 50065 ? 1 ? complete handling of protocol layers physical to mac ? programmable carrier frequencies in cenelec a-band from 9 to 95 khz; b ? band from 95 to 125 khz, in 10 hz steps ? half duplex ? data rate selectable: 300 ? 600 ? 1200 ? 2400 ? 4800 baud (@ 50 hz) 360 ? 720 ? 1440 ? 2880 ? 5760 baud (@ 60 hz) ? synchronization on mains ? repetition algorithm boost the robustness of communication ? sci port to application microcontroller ? sci baudrate selectable: 9.6 ? 19.2 ? 38.4 ? 115.2 kb ? power supply 3.3 v ? ambient temperature range: ? 40 c to +80 c ? these devices are pb ? free and are rohs compliant* typical applications ? arm: automated remote meter reading ? remote security control ? streetlight control ? transmission of alerts (fire, gas leak, water leak) *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. on e 3 arm see detailed ordering and shipping information in the package dimensions section on p age 27 of this data sheet. ordering information xxxx = date code y = plant identifier zz = traceability code http://onsemi.com marking diagrams 152 qfn52 8x8, 0.5p case 485m xxxxyzz ncn 49597 c597 ? 901 1 52
NCN49597 http://onsemi.com 2 application application example pc201 11120 .1 tx_out NCN49597 tx_enb zc_in ref_out rx_in rx_out xtal _i n xtal_out appli & metering c txd rxd br0 br1 resb vssa vss t_req vdd vdda 3v3_a 3v3_d 1:2 c 1 r 1 c 2 r 2 c dref c 16 c 17 3v3_a d 5 d 1 d 2 d 3 d 4 r 12 c 11 c 12 r 14 c 15 c 14 y 1 ncs5650 enable c 3 c 4 c 6 c 7 r 6 r 5 r 4 r 7 r 9 r 10 2 vcom +b ? b +a ? a outa outb 8 9 13 12 5 4 3 1 6 7 vcc 10 11 vee vuc 19 15 14 20 gnduc rlim vwarn 3v3_d 12v r 11 c 5 c 10 c 9 12v r 3 mains tr c 8 c 13 u 1 u 2 3v 3_d vdd1v8 r 8 sen ext_clk_e figure 1. typical application for the NCN49597s ? fsk modem figure 1 shows an s ? fsk plc modem build around NCN49597. for synchronization the line frequency is coupled in via a 1 m resistor. the schottky diode pair d 5 clamps the voltage within the input range of the zero cross detector. in the receive path a 2 nd order high pass filter blocks the mains frequency. the corner point defined by c 1 , c 2 , r 1 and r 2 is designed at 10 khz. in the transmit path a 3 th order low pass filter build around the ncs5650 power operational amplifier suppresses the 2 nd and 3 rd harmonics to be in line with the cenelec en 50065 ? 1 specification. the filter components are tuned for a space and mark frequency of 63.3 and 74 khz respectively. the output of the amplifier is coupled via a dc blocking capacitor c 10 to a 2:1 pulse transformer tr. the secondary of this transformer is coupled to the mains via a high voltage capacitor c 11 . high energetic transients from the mains are clamped by the protection diode combination d 3 , d 4 together with d 1 , d 2 . because the mains is not galvanic isolated care needs to be taken when interfacing to a microcontroller or a pc! table 1. external components list and description component function ? remark typ value tolerance unit c 1 , c 2 high pass receive filter 1.5 10% nf c 5 , c dref v ref_out ; v ref_out decoupling cap ? ceramic 1 ? 20 +80% f c 7 , c 9 , c 16 , c 17 decoupling block capacitor 100 ? 20 +80% nf c 3 tx_out coupling capacitor 470 20% nf c 4 low pass transmit filter 470 10% pf c 6 low pass transmit filter 68 10% pf c 8 low pass transmit filter 3 10% pf c 10 tx coupling cap; 1 a rms ripple @ 70 khz 10 20% f
NCN49597 http://onsemi.com 3 table 1. external components list and description component unit tolerance typ value function ? remark c 11 high voltage coupling capacitor; 630 v 220 20% nf c 12 zero cross noise suppression 100 20% pf c 13 , c 14 x ? tal load capacitor 22 20% pf c 15 decoupling block capacitor 1.8 v internal supply 1 ? 20 +80% f r 1 high pass receive filter 22 1% k r 2 high pass receive filter 11 1% k r 3 , r 9 , r 12, r 13 high pass receive filter; alarm current ; pull up 10 1% k r 4 low pass transmit filter 3,3 1% k r 5 low pass transmit filter 10 1% k r 6 low pass transmit filter 8,2 1% k r 7 low pass transmit filter 500 1% r 8 low pass transmit filter 3 1% k r 10 tx coupling resistor ; 0.5 w 0,47 1% r 11 zero cross coupling hiv 1 5% m d 1 , d 2 high current schottky clamp diodes mbra430 d 3 , d 4 tvs diodes p6smb6.8at3g d 5 double low current schottky clamp diode bas70 ? 04 y1 x ? tal 48 mhz tr 2:1 pulse transformer u1 plc modem NCN49597 u2 power operational amplifier ncs5650 table 2. absolute maximum ratings rating symbol min max unit absolute maximum ratings supply power supply pins vdd, vdda, vss, vssa absolute max. digital power supply v dd_absm v ss ? 0.3 3.9 v absolute max. analog power supply v dda_absm v ssa ? 0.3 3.9 v absolute max. difference between digital and analog power supply v dd ? v dda_absm ? 0.3 0.3 v absolute max. difference between digital and analog ground v ss ? v ssa_absm ? 0.3 0.3 v absolute maximum ratings non 5v safe pins non 5v safe pins: tx_out, alc_in, rx_in, rx_out, ref_out, zc_in, xin, xout, tdo, tdi, tck, tms, trstb, test absolute maximum input for normal digital inputs and analog inputs v in_absm v ss ? 0.3 v dd + 0.3 v absolute maximum voltage at any output pin v out_absm v ss ? 0.3 v dd + 0.3 v absolute maximum ratings 5v safe pins 5v safe pins: tx_enb, txd, rxd, br0, br1, io3 .. io11, resb absolute maximum input for digital 5v safe inputs v 5vs_absm v ss ? 0.3 6.0 v absolute maximum voltage at 5v safe output pin v out5v_absm v ss ? 0.3 3.9 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
NCN49597 http://onsemi.com 4 normal operating conditions operating ranges define the limits for functional operation and parametric characteristics of the device as described in the normal operating conditions section and for the reliability specifications as listed in detailed hardware description section. functionality outside these limits is not implied. total cumulative dwell time outside the normal power supply voltage range or the ambient temperature under bias, must be less than 0.1% of the useful life as defined in detailed hardware description section. table 3. operating ranges rating symbol min max unit power supply voltage range v dd 3.0 3.6 v ambient temperature t a ? 25 80 c extended ambient temperature on special request t a ? 40 80 c pin description qfn packaging amis49597 1 2 3 4 5 6 7 8 9 10 11 12 13 26 25 24 23 22 21 20 19 18 17 16 15 14 39 38 37 36 35 34 33 32 31 30 29 28 27 40 41 42 43 44 45 46 47 48 49 50 51 52 nc ref_out nc rx_in rx_out vssa vdda nc nc alc_in tx_out nc nc io8 io9 txd/pres xin xout vdd1v8 vss vdd txd io10 rxd sck sdi io7 io6 tms tck tdi tdo io0/rx_data io5 io4 io3 nc m50hz_in sdo csb t_req sen br1 br0 crc io11 test nc nc trst res tx_en figure 2. qfn pin ? out of NCN49597 (top view) table 4. NCN49597qfn pin function description pin no. pin name i/o type description 1 zc_in in a 50/60 hz input for mains zero cross detection 3..5, 12..15, 23, 34 io3 .. io11 in/out d, 5v safe general purpose i/o 6 rx_data out d, 5v safe data reception indication (open drain output) 7 tdo out d, 5v safe test data output 8 tdi in d, 5v safe test data input (internal pull down) 9 tck in d, 5v safe test clock (internal pull down) 10 tms in d, 5v safe test mode select (internal pull down) 11 trstb in d, 5v safe test reset bar (internal pull down, active low)
NCN49597 http://onsemi.com 5 table 4. NCN49597qfn pin function description pin no. description type i/o pin name 16 txd/pres out d, 5v safe output of transmitted data (txd) or pre_slot signal (pres) 17 xin in a xtal input (can be driven by an internal clock) 18 xout out a xtal output (output floating when xin driven by external clock) 19 vdd1v8 p 1v8 regulator output. foresee a decoupling capacitor 20 vss p digital ground 21 vdd p 3.3v digital supply 22 txd out d, 5v safe sci transmit output (open drain) 24 rxd in d, 5v safe sci receive input (schmitt trigger output) 25 sck out d spi interface external flash 26 sdi in d spi interface external flash 27 sdo out d spi interface external flash 28 csb in d spi interface external flash 29 t_req in d, 5v safe transmit request input 30 sen in d boot option 31 br1 in d, 5v safe sci baud rate selection 32 br0 in d, 5v safe sci baud rate selection 33 crc out d, 5v safe correct frame crc indication (open drain output) 35 resb in d, 5v safe master reset bar (schmitt trigger input, active low) 36 test in d hardware test enable (internal pull down) 37 tx_enb out d, 5v safe tx enable bar (open drain) 42 tx_out out a transmitter output 43 alc_in in a automatic level control input 46 vdda p 3.3v analog supply 47 vssa p analog ground 48 rx_out out a output of receiver low noise operational amplifier 49 rx_in in a positive input of receiver low noise operational amplifier 51 ref_out out a reference output for stabilization 2, 38..41, 44, 45,50, 52 nc pins 2, 38..41, 44, 45, 50, 52 are not connected. these pins need to be left open or connected to the gnd plane. p: power pin 5v safe: io that support the presence of 5v on bus line a: analog pin out: output signal d: digital pin in: input signal detailed pin description vdda vdda is the positive analog supply pin. nominal voltage is 3.3 v. a ceramic decoupling capacitor c da = 100 nf must be placed between this pin and the vssa. connection path of this capacitance to the vssa on the pcb should be kept as short as possible in order to minimize the serial resistance. ref_out ref_out is the analog output pin which provides the voltage reference used by the a/d converter. this pin must be decoupled to the analog ground by a 1 f ceramic capacitance c dref . the connection path of this capacitor to
NCN49597 http://onsemi.com 6 the vssa on the pcb should be kept as short as possible in order to minimize the serial resistance. vssa vssa is the analog ground supply pin. vdd vdd is the 3.3 v digital supply pin. a ceramic decoupling capacitor c dd = 100 nf must be placed between this pin and the vss. connection path of this capacitance to the vss on the pcb should be kept as short as possible in order to minimize the serial resistance. vss vss is the digital ground supply pin. figure 3: recommended layout of the placement of decoupling capacitors vdd1v8 this is an additional power supply pin to decouple an internal ldo regulator. the decoupling capacitor should be placed as close as possible to this output pin as illustrated in figure 4. rx_out rx_out is the output analog pin of the receiver low noise input op ? amp. this op ? amp is in a negative feedback configuration. rx_in rx_in is the positive analog input pin of the receiver low noise input op ? amp. together with rx_out and ref_out, an active high pass filter is realized. this filter removes the main frequency (50 or 60 hz) from the received signal. the filter characteristics are determined by external capacitors and resistors. a typical application schematic can be found in paragraph 50/60 hz suppression filter. zc_in zc_in is the mains frequency analog input pin. the signal is used to detect the zero cross of the 50 or 60 hz sine wave. this information is used, after filtering with the internal pll, to synchronize frames with the mains frequency. in case of direct connection to the mains it is advised to use a series resistor of 1 m in combination with two external clamp diodes in order to limit the current flowing through the internal protection diodes. rx_data rx_data is a 5 v compliant open drain output. an external pull ? up resistor defines the logic high level as illustrated in figure 4. a typical value for the pull ? up resistance ?r? is 10 k . the signal on this output depends on the status of the data reception. if NCN49597waits for configuration rx_data outputs a pulse train with a 10 hz frequency. after synchronization confirm time out rx_data = 0. if NCN49597is searching for synchronization rx_data = 1. pc20090722. 2 v ssd +5v output r figure 4. representation of 5v safe output tdo, tdi, tck, tms, and trstb all these pins are part of the jtag bus interface. the jtag interface is used during production test of the ic and will not be described here. input pins (tdi, tck, tms, and trstb) contain internal pull ? down resistance. tdo is an output. when not used, the jtag interface pins may be left floating. txd/pres txd/pres is the output for either the transmitting data (tx_data) or a synchronization signal with the time ? slots (pre_slot). txd/pres. more information can be found in paragraph local port. xin xin is the analog input pin of the oscillator. it is connected to the interval oscillator inverter gain stage. the clock signal can be created either internally with the external crystal and two capacitors or by connecting an external clock signal to xin. for the internal generation case, the two external capacitors and crystal are placed as shown in figure 5. for the external clock connection, the signal is connected to xin and xout is left unused.
NCN49597 http://onsemi.com 7 xtal_in pc20111118.1 xtal_out c x v ssa c x 48 mhz figure 5. placement of the capacitors and crystal with clock signal generated internally the crystal is a classical parallel resonance crystal of 48 mhz. the values of the capacitors c x are given by the manufacturer of the crystal. a typical value is 36 pf. the crystal has to fulfill impedance characteristics specified in the NCN49597data sheet. as an oscillator is sensitive and precise, it is advised to put the crystal as close as possible on the board and to ground the case. xout xout is the analog output pin of the oscillator. when the clock signal is provided from an external generator, this output must be floating. when working with a crystal, this pin cannot be used directly as clock output because no additional loading is allowed on the pin (limited voltage swing). txd txd is the digital output of the asynchronous serial communication (sci) unit. only half ? duplex transmission is supported. it is used to realize the communication between the NCN49597and the application microcontroller. the txd is an open drain io (5 v safe). external pull ? up resistances (typically 10 k ) are necessary to generate the 5 v level. see figure 4 for the circuit schematic. rxd this is the digital input of the asynchronous sci unit. only half ? duplex transmission is supported. this pin supports a 5 v level. it is used to realize the communication between the NCN49597and the application microcontroller. rxd is a 5 v safe input. t_req t_req is the transmission request input of the serial communication interface. when pulled low its initiate a local communication from the application micro controller to NCN49597. t_req is a 5 v safe input. see also paragraph error! reference source not found. . br1, br0 br0 and br1 are digital input pins. they are used to select the baud rate (bits/second) of the serial communication interface unit. the rate is defined according to error! reference source not found. . the values are taken into account after a reset, hardware or software. modification of the baud rate during function is not possible. br0 and br1 are 5 v safe. crc crc is a 5 v compliant open drain output. an external pull ? up resistor defines the logic high level as illustrated in figure 4. a typical value for this pull ? up resistance ?r? is 10 k . the signal on this output depends on the cyclic redundancy code result of the received frame. if the cyclic redundancy code is correct crc = h during the pause between two time slots. resb resb is a digital input pin. it is used to perform a hardware reset of the NCN49597. this pin supports a 5 v voltage level. the reset is active when the signal is low (0 v). test test is a digital input pin with internal pull down resistor used to enable the hardware test mode of the chip. when test is left open or forced to ground normal mode is enabled. when test is forced to vdd the hardware test mode is enabled. this mode is used during production test of the ic and will not be described here. test pin is not 5 v safe. tx_enb tx_enb is a digital output pin. it is low when the transmitter is activated. the signal is available to turn on the line driver. tx_enb is a 5 v safe with open drain output, hence a pull ? up resistance is necessary achieve the requested voltage level associated with a logical one. see also figure 4 for reference. tx_out tx_out is the analog output pin of the transmitter. the provided signal is the s ? fsk modulated frames. a filtering operation must be performed to reduce the second and third order harmonic distortion. for this purpose an active filter is suggested. see also paragraph transmitter output tx_out. alc_in alc_in is the automatic level control analog input pin. the signal is used to adjust the level of the transmitted signal. the signal level adaptation is based on the ac component. the dc level on the alc_in pin is fixed internally to 1.65 v. comparing the peak voltage of the ac signal with two internal thresholds does the adaptation of the gain. low threshold is fixed to 0.4 v. a value under this threshold will result in an increase of the gain. the high threshold is fixed to 0.6 v. a value over this threshold will result in a decrease of the gain. a serial capacitance is used to block the dc components. the level adaptation is performed during the transmission of the first two bits of a new frame. eight successive adaptations are performed. see
NCN49597 http://onsemi.com 8 also paragraph amplifier with automatic level control (alc). sck, sdi, sdo, csb these signals from the spi interface to an optional external flash. see reference 1. electrical characteristics dc and ac characteristics oscillator: pin xin, xout in production the actual oscillation of the oscillator and duty cycle will not be tested. the production test will be based on the static parameters and the inversion from xin to xout in order to guarantee the functionality of the oscillator. table 5. oscillator parameter test conditions symbol min typ max unit crystal frequency (note 1) f clk ? 100 ppm 48 +100 ppm mhz duty cycle with quartz connected (note 1) 40 60 % start ? up time (note 1) t startup 50 ms load capacitance external crystal (note 1) c l 18 pf series resistance external crystal (note 1) r s 20 40 80 maximum capacitive load on xout xin used as clock input cl xout 50 pf low input threshold voltage xin used as clock input vil xout 0.3 v dd v high input threshold voltage xin used as clock input vih xout 0.7 v dd v low output voltage xin used as clock input, xout = 2 ma vol xout 0.3 v high input voltage xin used as clock input voh xout v dd ? 0.3 v 1. guaranteed by design. maximum allowed series loss resistance is 80
NCN49597 http://onsemi.com 9 zero cross detector and 50/60 hz pll: pin zc_in table 6. zero cross detector and 50/60 hz pll parameter test conditions symbol min typ max unit maximum peak input current imp zc_in ? 20 20 ma maximum average input current during 1 ms imavg zc_in ? 2 2 ma mains voltage (ms) range with protection resistor at zc_in v mains 90 550 v rising threshold level (note 2) vir zc_in 1.9 v falling threshold level (note 2) vif zc_in 0.9 v hysteresis (note 2) vhy zc_in 0.4 v lock range for 50 hz (note 3) mains_freq = 0 (50 hz) flock 50hz 45 55 hz lock range for 60 hz (note 3) mains_freq = 0 (60 hz) flock 60hz 54 66 hz lock time (note 3) mains_freq = 0 (50 hz) tlock 50hz 15 s lock time (note 3) mains_freq = 0 (60 hz) tlock 60hz 20 s frequency variation without going out of lock (note 3) mains_freq = 0 (50 hz) df 60hz 0.1 hz/s frequency variation without going out of lock (note 3) mains_freq = 0 (60 hz) df 50hz 0.1 hz/s jitter of chip_clk (note 3) jitter chip_clk ? 25 25 s 2. measured relative to vss 3. these parameters will not be measured in production since the performance is totally dependent of a digital circuit which will be gua ranteed by the digital test patterns.
NCN49597 http://onsemi.com 10 transmitter external parameters: pin tx_out, alc_in, tx_enb to guarantee the transmitter external specifications the tx_clk frequency must be 12 mhz 100 ppm. table 7. transmitter external parameters parameter test conditions symbol min typ max unit maximum peak output level f tx_out = 23 ? 75 khz f tx_out = 95 khz level control at max. output v tx_out 0.85 0.76 1.15 1.22 vp second order harmonic distortion f tx_out = 95 khz level control at max. output hd2 ? 54 db third order harmonic distortion f tx_out = 95 khz level control at max. output hd3 ? 53 db frequency accuracy of the gener- ated sine wave (notes 4 and 6) df tx_out 30 hz capacitive output load at pin tx_out (note 4) cl tx_out 20 pf resistive output load at pin tx_out rl tx_out 5 k turn off delay of tx_enb output (note 5) td tx_enb 0.25 0.5 ms automatic level control attenuation step alc step 2.9 3.1 db maximum attenuation alc range 20.3 21.7 db low threshold level on alc_in vtl alc_in ? 0.46 ? 0.36 v high threshold level on alc_in vth alc_in ? 0.68 ? 0.54 v input impedance of alc_in pin r alc_in 111 189 k power supply rejection ration of the transmitter section psrr tx_out 10 (note 7) 35 (note 8) db 4. this parameter will not be tested in production. 5. this delay corresponds to the internal transmit path delay and will be defined during design. 6. taking into account the resolution of the dds and an accuracy of 100ppm of the crystal. 7. a sinusoidal signal of 10 khz and 100 mvpp is injected between vdda and vssa. the digital ad converter generates an idle patt ern. the signal level at tx_out is measured to determine the parameter. 8. a sinusoidal signal of 50 hz and 100 mvpp is injected between vdda and vssa. the digital ad converter generates an idle patte rn. the signal level at tx_out is measured to determine the parameter. the lpf filter + amplifier must have a frequency characteristic between the limits listed below. the absolute output level depends on the operating condition. in production the measurement will be done for relative output levels where the 0 db reference value is measured at 50 khz with a signal amplitude of 100 mv. table 8. transmitter frequency characteristics frequency (khz) attenuation unit min max 10 ? 0.5 0.5 db 95 ? 1.3 0.5 db 130 ? 4.5 ? 2.0 db 165 ? 3.0 db 330 ? 18.0 db 660 ? 36.0 db 1000 ? 50 db 2000 ? 50 db
NCN49597 http://onsemi.com 11 receiver external parameters: pin rx_in, rx_out, ref_out table 9. receiver external parameters parameter test conditions symbol min typ max unit input offset voltage 42 db agc gain = 42 db v offs_rx_in 5 mv input offset voltage 0 db agc gain = 0 db v offs_rx_in 50 mv max. peak input voltage (corres- ponding to 62.5% of the sd full scale) agc gain = 0 db (note 9) v max_rx_in 0.85 1.15 vp input referred noise of the analog receiver path agc gain = 42 db (notes 9 and 10) nf rx_in 150 nv/ hz input leakage current of receiver input i le_rx_in ? 1 1 a max. current delivered by ref_out i max_ref_out ? 300 300 ma power supply rejection ratio of the receiver input section agc gain = 42 db (note 11) psrr lpf_out 10 db agc gain = 42 db (note 12) 35 agc gain step agc step 5.7 6.3 db agc range agc range 39.9 44.1 db analog ground reference output voltage v ref_out 1.52 1.78 v signal to noise ratio at 62.5 % of the sd full scale (notes 9 and 13) sn ad_out 54 db clipping level at the output of the gain stage (rx_out) v clip_agc_in 1.15 1.65 vp 9. input at rx_in, no other external components. 10. characterization data only. not tested in production. 11. a sinusoidal signal of 10 khz and 100 mvpp is injected between vdda and vssa. the signal level at the differential lpf_out a nd ref_out output is measured to determine the parameter. 12. a sinusoidal signal of 50 hz and 100 mvpp is injected between vdda and vssa. the signal level at the differential lpf_out ou tput is measured to determine the parameter. 13. these parameters will be tested in production with an input signal of 95 khz and 1 vp by reading out the digital samples at the point ad_out with the default settings of t_rx_mod[7], sdmod_typ, dec_typ, and cor_f_ena. the agc gain is switched to 0 db. the receive lpf filter + agc + low noise amplifier must have a frequency characteristic between the limits listed below. the absolute output level depends on the operating condition. table 10. receiver frequency characteristics frequency (khz) attenuation unit min max 10 ? 0.5 0.5 db 95 ? 1.3 0.5 db 130 ? 4.5 ? 2.0 db 165 ? 3.0 db 330 ? 18.0 db 660 ? 36.0 db 1000 ? 50 db 2000 ? 55 db
NCN49597 http://onsemi.com 12 power ? on ? reset (por) table 11. power ? on ? reset parameter test conditions symbol min typ max unit por threshold v por 1.7 2.7 v power supply rise time 0 to 3v t rpor 1 ms digital outputs: tdo, clk_out table 12. digital outputs: tdo, clk_out parameter test conditions symbol min typ max unit low output voltage i xout = 4 ma v ol 0.4 v high output voltage i xout = ? 4 ma v oh 0.85 v dd v digital outputs with open drain: tx_enb, txd table 13. digital outputs with open drain: tx_enb, txd, rx_data, crc, t_req parameter test conditions symbol min typ max unit low output voltage i xout = 4 ma v ol 0.4 v digital inputs: br0, br1 table 14. digital inputs: br0, br1 parameter test conditions symbol min typ max unit low input level v il 0.2 v dd v high input level 0 to 3 v v ih 0.8 v dd v input leakage current i leak ? 10 10 a digital inputs with pull down: tdi, tms, tck, trstb, test table 15. digital inputs with pull down: tdi, tms, tck, trstb, test parameter test conditions symbol min typ max unit low input level v il 0.2 v dd v high input level v ih 0.8 v dd v pull down resistor (note 14) r pu 7 50 k 14. measured around a bias point of v dd /2. digital schmitt trigger inputs: rxd, resb table 16. digital schmitt trigger inputs: rxd, resb parameter test conditions symbol min typ max unit rising threshold level v t+ 0.80 v dd v falling threshold level v t ? 0.2 v dd v input leakage current i leak ? 10 10 a
NCN49597 http://onsemi.com 13 current consumption table 17. current consumption parameter test conditions symbol min typ max unit current consumption in receive mode current through v dd and v dda (note 15) i rx 60 80 ma current consumption in transmit mode current through v dd and v dda (note 15) i tx 60 80 ma current consumption when resb = 0 current through v dd and v dda (note 15) i reset 4 ma 15. f clk = 48 mhz. introduction general description the NCN49597 is a single chip half duplex s ? fsk modem dedicated to power line carrier (plc) data transmission on low ? or medium ? voltage power lines. the device of fers complete handling of the protocol layers from the physical up to the mac. NCN49597 complies with the cenelec emc standard en 50065 ? 1 and the iec 61334 ? 5 ? 1 standards. it operates from a single 3.3 v power supply and is interfaced to the power line by an external power driver and transformer. an internal pll is locked to the mains frequency and is used to synchronize the data transmission at data rates of 300, 600, 1200, 2400 and 4800 baud for a 50 hz mains frequency, or 360, 720, 1440, 2880 and 5760 baud for a 60 hz mains frequency. in both cases this corresponds to 3, 6, 12 or 24 data bits per half cycle of the mains period. s ? fsk is a modulation and demodulation technique that combines some of the advantages of a classical spread spectrum system (e.g. immunity against narrow band interferers) with the advantages of the classical fsk system (low complexity). the transmitter assigns the space frequency f s to ?data 0? and the mark frequency f m to ?data 1?. the difference between s ? fsk and the classical fsk lies in the fact that f s and f m are now placed far from each other, making their transmission quality independent from each other (the strengths of the small interferences and the signal attenuation are both independent at the two frequencies). the frequency pairs supported by the NCN49597 are in the range of 9 ? 150 khz with a typical separation of 10 khz. the conditioning and conversion of the signal is performed at the analog front ? end of the circuit. the further processing of the signal and the handling of the protocol is digital. at the back ? end side, the interface to the application is done through a serial interface. the digital processing of the signal is partitioned between hardwired blocks and a microprocessor block. the microprocessor is controlled by firmware. where timing is most critical, the functions are implemented with dedicated hardware. for the functions where the timing is less critical, typically the higher level functions, the circuit makes use of the arm microprocessor core. the processor runs dsp algorithms and, at the same time, handles the communication protocol. the communication protocol, in this application, contains the mac = medium access control layer. the program running on the microprocessor is stored into rom. the working data necessary for the processing is stored in an internal ram. at the back ? end side the link to the application hardware is provided by a serial communication interface (sci). the sci is an easy to use serial interface, which allows communication between an external processor used for the application software and the NCN49597 modem. the sci works on two wires: txd and rxd. baud rate is programmed by setting 2 bits (br0, br1). because the low protocol layers are handled in the circuit, the NCN49597 provides an innovative architectural split. thanks to this, the user has the benefit of a higher level interface of the link to the plc medium. compared to an interface at the physical level, the NCN49597 allows faster development of applications. the user just needs to send the raw data to the NCN49597 and no longer has to take care of the protocol detail of the transmission over the specific medium. this last part represents usually 50% of the software development costs.
NCN49597 http://onsemi.com 14 minor user type major user type pc201111 12.2 spy application NCN49597 in monitor mode test application NCN49597 in test mode client application NCN49597 in master mode server application NCN49597 in slave mode server application NCN49597 in slave mode figure 6. application examples NCN49597 is intended to connect equipment using distribution line carrier (dlc) communication. it serves two major and two minor types of applications: ? major types: ? master or client: a master is a client to the data served by one or many slaves on the power line. it collects data from and controls the slave devices. a typical application is a concentrator system ? slave or server: a slave is a server of the data to the master. a typical application is an electricity meter equipped with a plc modem. ? minor type: ? spy or monitor: spy or monitor mode is used to only listen to the data that comes across the power line. only the physical layer frame correctness is checked. when the frame is correct, it is passed to the external processor. ? test mode: the software test mode is used to test the compliance of a plc modem conforms to cenelec. en 50065 ? 1 by a continuous broadcast of f s or f m .
NCN49597 http://onsemi.com 15 functional description the block diagram below represents the main functional units of the NCN49597: communication controller arm risc core serial comm. interface local port test control por watchdog timer 1 & 2 spi interrupt control data ram program rom aaf agc a/d ref s ? fsk demodulator receiver (s ? fsk demodulator) clock and control zero crossing pll osc clock generator & timer transmit data & sine synthesizer d/ a lp filter transmitter (s ? fsk modulator) rx_data resb jtag i /f test tx_enb tx_out alc_in rx_out rx_in ref_out m50hz_in xin xout vdda vssa vddd vssd NCN49597 pc20111019.2 to power amplifier from line coupler to application micro controller txd rxd t_req br0 br1 crc tx_data / pre_slot 5 vdd1v8 io[9:3] 5 spi i/f 5 figure 7. s ? fsk modem NCN49597 block diagram transmitter the NCN49597 transmitter function block prepares the communication signal which will be sent on the transmission channel during the transmitting phase. this block is connected to a power amplifier which injects the output signal on the mains through a line ? coupler. receiver the analog signal coming from the line ? coupler is low pass filtered in order to avoid aliasing during the conversion. then the level of the signal is automatically adapted by an automatic gain control (agc) block. this operation maximizes the dynamic range of the incoming signal. the signal is then converted to its digital representation using sigma delta modulation. from then on, the processing of the data is done in a digital way. by using dedicated hardware, a direct quadrature demodulation is performed. the signal demodulated in the base band is then low pass filtered to reduce the noise and reject the image spectrum. clock and control according to the iec 61334 ? 5 ? 1 standard, the frame data is transmitted at the zero cross of the mains voltage. in order to recover the information at the zero cross, a zero cross detection of the mains is performed. a phase ? locked loop (pll) structure is used in order to allow a more reliable reconstruction of the synchronization. this pll permits as well a safer implementation of the ?repetition with credit? function (also known as chorus transmission). the clock generator makes use of a precise quartz oscillator master. the clock signals are then obtained by the use of a programmed division scheme. the support circuits are also contained in this block. the support circuits include the necessary blocks to supply the references voltages for the ad and da converters, the biasing currents and power supply sense cells to generate the right power off and startup conditions.
NCN49597 http://onsemi.com 16 48 bit @ 2400 baud 20 ms t pc20100609.1 figure 8. data stream is in sync with zero cross of the mains (example for 50 hz) communication controller the communication controller block includes the micro ? processor, its peripherals: ram, rom, uart, timer, and the power on reset. the processor uses the arm reduced instruction set computer (risc) architecture optimized for io handling. for most of the instructions, the machine is able to perform one instruction per clock cycle. the microcontroller contains the necessary hardware to implement interrupt mechanisms, timers and is able to perform byte multiplication over one instruction cycle. the microcontroller is programmed to handle the physical layer (chip synchronization), and the mac layer conform to iec 61334 ? 5 ? 1. the program is stored in a masked rom. the ram contains the necessary space to store the working data. the back ? end interface is done through the serial communication interface block. this back ? end is used for data transmission with the application micro controller (containing the application layer for concentrator, power meter, or other functions) and for the definition of the modem configuration. local port the controller uses 3 output ports to inform about the actual status of the plc communication. rx_data indicates if receiving is in progress, or if NCN49597 is waiting for synchronization, or of it configures. crc indicates if the received frames are valid (crc = ok). txd/pres is the output for either the transmitting data (tx_data) or a synchronization signal with the time ? slots (pre_slot). serial communication interface the local communication is a half duplex asynchronous serial link using a receiving input (rxd) and a transmitting output (txd). the input port t_req is used to manage the local communication with the application micro controller and the baud rate can be selected depending on the status of two inputs br0, br1. these two inputs are taken in account after an NCN49597 reset. thus when the application micro controller wants to change the baud rate, it has to set the two inputs and then provoke a reset. detailed hardware description clock and control according to the iec 61334 ? 5 ? 1 standard, the frame data is transmitted at the zero cross of the mains voltage. in order to recover the information at the zero cross, a zero cross detection of the mains is performed. a phase ? locked loop (pll) structure is used in order to allow a more reliable reconstruction of the synchronization. the output of this block is the clock signal chip_clk, 8 times over sampled with the bit rate. the oscillator makes use of precise 48 mhz quartz. this clock signal together with chip_clk is fed into the clock generator and time block. here several internal clock signals and timings are obtained by the use of a programmed division scheme.
NCN49597 http://onsemi.com 17 clock and control zero crossing pll osc clock generator & timer zc_in xin xout pc20090619.4 bit_clk byte_clk frame_clk pre_byte_clk pre_frame_clk pre_slot chip_clk figure 9. clock and control block zero cross detector zc_in is the mains frequency analog input pin. the signal is used to detect the zero cross of the 50 or 60 hz sine wave. this information is used, after filtering with the internal pll, to synchronize frames with the mains frequency. in case of direct connection to the mains it is advised to use a series resistor of 1 m in combination with two external schottky clamp diodes in order to limit the current flowing through the internal protection diodes. from mains clock & control zc_in zerocross pll chip_clk debounce filter 3v3_a 1m pc20100608.1 100 pf bas70 ? 04 figure 10. zero cross detector with falling edge de ? bounce filter the zero cross detector output is logic zero when the input is lower than the falling threshold level and a logic one when the input is higher than the rising threshold level. the falling edges of the output of the zero cross detector are de ? bounced by a period between 0.5 ms and 1 ms. the rising edges are not de ? bounced.
NCN49597 http://onsemi.com 18 t 10 ms v mains zerocross t zcd vir zc _in pc20090620 .1 vif zc _in t debounce = 0,5 .. 1 ms figure 11. zero cross detector signals and timing (example for 50 hz) 50/60 hz pll the output of the zero cross detector is used as an input for a pll. the pll generates the clock chip_clk which is 8 times the bit rate and which is in phase with the rising edge crossings. the pll locks on the zero cross from negative to positive phase. the bit rate is always an even multiple of the mains frequency, so following combinations are possible: table 18. chip_clk in function of selected baud rate and mains frequency baud[1:0] mains_freq baudrate chip_clk 00 50 hz 300 2400 hz 01 600 4800 hz 10 1200 9600 hz 11 2400 19200 hz 00 60 hz 360 2880 hz 01 720 5760 hz 10 1440 11520 hz 11 2880 23040 hz in case no zero crossings are detected the pll freezes its internal timers in order to maintain the chip_clk timing.
NCN49597 http://onsemi.com 19 6 bit @ 300 baud t 10 ms v mains zerocross t zcd vir zc _in chip _clk pc 20090 619 .3 pll in lock start of physical preframe (*) *the start of the physical subframe is shifted back with r_zc_adjust[7:0] x 26 s = t zcd to compensate for the zero cross delay. figure 12. zero cross adjustment to compensate for zero cross delay (example for 50 hz) the phase difference between the zero cross of the mains and chip_clk can be tuned. this opens the possibility to compensate for external delay t zcd (e.g. opto coupler) and for the 1.9 v positive threshold vir zc_in of the zero cross detector. this is done by pre ? loading the pll counter with a number value stored in register r_zc_adjust[7:0]. the adjustment period or granularity is 26 s. the maximum adjustment is 255 x 26 s = 6.6 ms which corresponds with 1/3rd of the 50 hz mains sine period. table 19. zero cross delay compensation r_zc_adjust[7:0] compensation 0000 0000 0 s 0000 0001 26 s 0000 0010 52 s 0000 0011 78 s 1111 1101 6589 s 1111 1110 6615 s 1111 1111 6641 s oscillator the oscillator works with a standard parallel resonance crystal of 48 mhz. xin is the input to the oscillator inverter gain stage and xout is the output.
NCN49597 http://onsemi.com 20 xtal_in pc20111118.1 xtal_out c x v ssa c x 48 mhz figure 13. placement of the capacitors and crystal with clock signal generated internally for correct functionality the external circuit illustrated in figure 13 must be connected to the oscillator pins. for a crystal requiring a parallel capacitance of 18 pf c x must be around 36 pf. (values of capacitors are indicative only and are given by the crystal manufacturer). to guarantee startup the series loss resistance of the crystal must be smaller than 60 . the oscillator output f clk = 48 mhz is the base frequency for the complete ic. the clock frequency for the arm f arm = f clk. the clock for the transmitter, f tx_clk is equal to f clk / 4 or 12 mhz. all the transmitter internal clock signals will be derived from f tx_clk . the clock for the receiver, f rx_clk is equal to f clk / 8 or 6 mhz. all the receiver internal clock signals will be derived from f rx_clk. clock generator and timer the chip_clk and f clk are used to generate a number of timing signals used for the synchronization and interrupt generation. the timing generat ion has a fixed repetition rate which corresponds to the length of a physical subframe. (see paragraph error! reference source not found. ) the timing generator is the same for transmit and receive mode. when NCN49597 switches from receive to transmit and back from transmit to receive, the r_chip_cnt counter value is maintained. as a result all timing signals for receive and transmit have the same relative timing. the following timing signals are defined as: bit_clk 63 64 65 2871 2872 1 0 2879 2 3 4 5 6 7 8 9 chip_clk byte_clk frame_clk pre_frame_clk pre_byte_clk r_chip_cnt pre_slot pc20090619.1 start of the physical subframe figure 14. timing signals chip_clk : is the output of the pll and 8 times the bit rate on the physical interface. see also paragraph 50/60 hz pll . bit_clk: is active at counter values 0, 8, 16, .. 2872 and inactive at all other counter values. this signal is used to indicate the transmission of a new bit. byte_clk : is active at counter values 0, 64, 128, .. 2816 and inactive at all other counter values. this signal is used to indicate the transmission of a new byte.
NCN49597 http://onsemi.com 21 frame_clk : is active at counter values 0 and inactive at all other counter values. this signal is used to indicate the transmission or reception of a new frame. pre_byte_clk is a signal which is 8 chip_clk sooner than byte_clk. this signal is used as an interrupt for the internal microcontroller and indicates that a new byte for transmission must be generated. pre_frame_clk is a signal which is 8 chip_clk sooner than frame_clk. this signal is used as an interrupt for the internal microcontroller and indicates that a new frame will start at the next frame_clk. pre_slot is logic 1 between the rising edge of pre_frame_clk and the rising edge of frame_clk. this signal can be provided at the digital output pin txd/pres when r_conf[7] = 0 (see paragraph local port and error! reference source not found. , field r_conf_txd_pres_sel ) and can be used by the external host controller to synchronize its software with the frame_clk of NCN49597. transmitter path description (s ? fsk modulator) for the generation of the space and mark frequencies, the direct digital synthesis (dds) of the sine wave signals is performed under the control of the microprocessor. after a signal conditioning step, a digital to analog conversion is performed. as for the receive path, a sigma delta modulation technique is used. in the analog domain, the signal is low pass filtered, in order to remove the high frequency quantization noise, and passed to the automatic level controller (alc) block, where the level of the transmitted signal can be adjusted. the determination of the signal level is done through the sense circuitry. transmitter(s ? fsk modulator ) pc20091019.1 arm interface & control tx_out transmit data & sine synthesizer d/a lp filter alc control alc_in to receiver f mi f mq f si f sq tx_en figure 15. transmitter block diagram arm interface and control the interface with the arm consists in a 8 ? bit data registers r_tx_data, 2 control registers r_tx_ctrl and r_alc_ctrl, a flag tx_rxb defining transmit and receive and 2 16 ? bit wide frequency step registers r_fm and r_fs defining f m (mark frequency = data 1) and f s (space frequency = data 0). all these registers are memory mapped. some of them are for internal use only and cannot be accessed by the user. processing of the physical frame (preamble, mac address, crc) is done by the arm. sine wave generator a sine wave is generated with a direct digital synthesizer dds. the synthesizer generates in transmission mode a sine wave either for the space frequency (f s , data 0) or for the mark frequency (f m , data1). in reception the synthesizer generates the sine and cosine waves for the mixing process, f si , f sq , f mi , f mq (space and mark signals in phase and quadrature). the space and mark frequencies are defined in an individual step 16 bit wide register. table 20. fs and fm step registers arm register hard reset soft reset description r_fs[15:0] 0000h 0000h step register for the space frequency f s r_fm[15:0] 0000h 0000h step register for the mark frequency f m
NCN49597 http://onsemi.com 22 the space and mark frequency can be calculated as: ? f s = r_fs[15:0]_dec x f dds /2 18 ? f m = r_fm[15:0]_dec x f dds /2 18 or the content of both r_fs[15:0] and r_fm[15:0] are defined as: ? r_fs[15:0]_dec = round(2 18 x f s /f dds ) ? r_fm[15:0]_dec = round(2 18 x f m /f dds ) ? where f dds = 3 mhz is the direct digital synthesizer clock frequency. after a hard or soft reset or at the start of the transmission (when tx_rxb goes from 0 to 1) the phase accumulator must start at it?s 0 phase position, corresponding with a 0 v output level. when switching between f m and f s the phase accumulator must give a continuous phase and not restart from phase 0 when NCN49597 goes into receive mode (when tx_rxb goes from 1 to 0) the sine wave generator must make sure to complete the active sine period. the control logic for the transmitter generates a signal tx_enb to enable the external power amplifier. tx_enb is 1 when the NCN49597 is in receive mode. tx_enb is 0 when NCN49597is in transmit mode. when going from transmit to receive mode (tx_rxb goes from 1 to 0) the tx_enb signal is kept active for a short period of t dtx_enb . the control logic for the transmitter generates a signal tx_data which corresponds to the transmitted s ? fsk signal. when transmitting f m tx_data is logic 1. when transmitting f s tx_data is logic 0. when the transmitter is not enabled (tx_rxb = 0) tx_data goes to logic 1 at the next bit_clk. pc200 90610.1 tx_data tx_rxb t dtx_enb bit_clk tx_enb tx_out figure 16. tx_enb timing da converter a digital to analog converter converts the sine wave digital word to a pulse density modulated (pdm) signal. the pdm signal is converted to an analog signal with a first order switched capacitor filter. low pass filter a 3 rd order continuous time low pass filter in the transmit path filters the quantization noise and noise generated by the ? da converter. the typical corner frequency f ? 3db = 138 khz and is internally trimmed to compensate for process variation. this filter can be tuned to f ? 3db = 1508 khz as described in reference [1]. amplifier with automatic level control (alc) the pin alc_in is used for level control of the transmitter output level. first peak detection is done. the peak value is compared to two thresholds levels: vtl alc_in and vth alc_in . the result of the peak detection is used to control the setting of the level of tx_out. the level of tx_out can be attenuated in 8 steps of 3 db typical. after hard or soft reset the level is set at minimum level (maximum attenuation) when going to reception mode (when tx_rxb goes from 1 to 0) the level is kept in memory so that the next transmit frame starts with the old level. the evaluation of the level is done during 1 chip_clk period. depending on the value of peak level on alc_in the attenuation is updated: ? vp alc_in < vtl alc : increase the level with one 6 db step ? vtl alc vp alc_in vth alc : don?t change the level ? vp alc_in > vth alc : decrease the level with one 6 db step
NCN49597 http://onsemi.com 23 the gain changes in the next chip_clk period. an evaluation phase and a level adjustment take 2 chip_clk periods. alc operation is enabled only during the first 16 chip_clk cycles after a hard or soft reset or after going into transmit mode. the automatic level control can be disabled by setting register r_alc_ctrl[3] = 1. in this case the transmitter output level is fixed to the programmed level in the register r_alc_ctrl[2:0]. see reference 1. table 21. fixed transmitter output attenuation alc_ctrl[2:0] attenuation 000 0 db 001 ? 3 db 010 ? 6 db 011 ? 9 db 100 ? 12 db 101 ? 15 db 110 ? 18 db 111 ? 21 db remark: transmitter output tx_out the transmitter output is dc coupled to the tx_out pin. because the complete analog part of NCN49597 is referenced to the analogue ground ref_out, a decoupling capacitor c 1 is needed when connecting NCN49597 to external circuitry working with another ground. to suppress the second and third order harmonic of the generated s ? fsk signal it is recommended to use a 2 nd or 4 th order low pass filter. in figure 17 a mfb topology of a 2 nd order filter is illustrated. alc control alc _in transmitter (s ? fsk modulator ) pc 20091216.1 arm interface & control tx_out lp filter tx_en to tx power output stage from line driver c 1 r 1 v ssa c 2 r 2 r 3 c 3 c 4 r 4 figure 17. tx_out filter receiver path description receiver block diagram the receiver takes in the analog signal from the line coupler, conditions it and demodulates it in a data ? stream to the communication controller. the operation mode and the baud rate are made according to the setting in r_conf, r_fs and r_fm. the receive signal is applied first to a high pass filter. therefore NCN49597 has a low noise operational amplifier at the input stage which can be used to make a high pass active filter to attenuate the mains frequency. this high pass filter output is followed by a gain stage which is used in an automatic gain control loop. this block also performs a single ended input to differential output conversion. this gain stage is followed by a continuous time low pass filter to limit the bandwidth. a 4 th order sigma delta converter converts the analog signal to digital samples. a quadrature demodulation for f s and f m is than performed by an internal dsp, as well the handling of the bits and the frames.
NCN49597 http://onsemi.com 24 rx_out rx_in ref_out pc20090610.2 low noise opamp ref 1,65 v to digital receiver (analog path) gain lpf 4th order ad from digital figure 18. analog path of the receiver pc20110610.3 abs value accu receiver (digital path) 1 st decimator noise shaper compen ? sator agc control from analog to gain f si f mq f sq sliding filter sliding filter sliding filter sliding filter quadrature demodulator f s f m 2 nd decimator 2 nd decimator 2 nd decimator 2 nd decimator i m q m i s q s f mi from transmitter f mq f si f sq figure 19. digital path of the receiver adc and quadrature demodulation 50/60 hz suppression filter NCN49597 receiver input provides a low noise input operational amplifier in a follower configuration which can be used to make a 50/60 hz suppression filter with a minimum number of external components. pin rx_in is the positive input and rx_out is the output of the input low noise operational amplifier. ref_out is the analog output pin which provides the voltage reference (1.65 v) used by the a/d converter. this pin must be decoupled from the analog ground by a 1 f ceramic capacitance (c dref ). it is not allowed to load this pin. pc20090722.1 c 1 r 1 c 2 r 2 c dref rx_out rx_in ref_out received signal v ssa low noise opamp ref 1,65 v to agc receiver (s ? fsk demodulator) 2 3 4 v in figure 20. external component connection for 50/60 hz suppression filter rx_in is the positive analog input pin of the receiver low noise input op ? amp. together with the output rx_out an active high pass filter is realized. this filter removes the main frequency (50 or 60 hz) from the received signal. the filter characteristics are determined by external capacitors and resistors. typical values are given in t able 27. for these values and after this filter, a typical attenuation of 85 db at 50 hz is obtained. figure 21 represents external components connection. in a typical application the coupling transformer in combination with a parallel capacitance forms a high pass filter with a typical attenuation of 60 db. the combined effect of the two filters
NCN49597 http://onsemi.com 25 decreases the voltage level of 230 vrms at the mains frequency well below the sensitivity of the NCN49597. t frequency (hz) 10 100 1k 10k 100k vin/vrx_out (db) ? 140 ? 100 ? 60 ? 20 20 figure 21. transfer function of 50 hz suppression circuit table 22. value of the resistors and capacitors component value unit c 1 1.5 nf c 2 1.5 nf c dref 1 f r 1 22 k r 2 11 k remark: the analog part of NCN49597 is referenced to the internal analog ground ref_out = 1.65 v (typical value). if the external circuitry works with a different analogue reference level one must be sure to place a decoupling capacitor. auto gain control (agc) the receiver path has a gain stage which is used for automatic gain control. the gain can be changed in 8 steps of 6 db. the control of the agc is done by a digital circuit which measures the signal level after the ad converter, and regulates the average signal in a window around a percentage of the full scale. the agc works in 2 cycles: a measurement cycle at the rising edge of the chip_clk and an update cycle starting at the next chip_clk. low noise anti aliasing filter the receiver has a 3 rd order continuous time low pass filter in the signal path. this filter is in fact the same block as in the transmit path which can be shared because NCN49597works in half duplex mode. the typical corner frequency f ? 3db = 138 khz and is internally trimmed to compensate for process variation. a/d converter the output of the low pass filter is input for an analog 4 th order sigma ? delta converter. the dac reference levels are supplied from the reference block. the digital output of the converter is fed into a noise shaping circuit blocking the quantization noise from the band of interest, followed by a decimation and a compensation step. quadrature demodulator the quadrature demodulation block takes the ad signal and mixes it with the in ? phase and quadrature phase of the f s and f m carrier frequencies. after a low pass filter and rectification the mixer output signals are further processed in software. there the accumulation over a period of chip_clk is done which results in the discrimination of data 0 and data 1.
NCN49597 http://onsemi.com 26 bit sync at the transmit side the data ? stream is in sync and in phase with the zero crossing of the mains. the complex impedance of the power line together with propagation delay in the zero cross detector and loop delay in the rx ? filter circuitry will cause a shift between the physical transmitted bit and the received s ? fsk signal as illustrated in figure 23. mains transmitted bit stream bit delay transmission over the power line modulation bit 0 bit1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 t pc20101119 .1 figure 22. bit delay cause by transmission over a power line to compensate for this delay between physical and demodulated bit a synchro bit value is introduced. it shifts forward the hardware demodulating process up to 7 chip clocks. see figure 24. bit 0 bit1 bit 2 chip_clk sbv[2:0] = 0 sbv[2:0] = 3 pc20101119 .2 figure 23. compensation for bit delay by shifting forward the start of the demodulating process the synchro bit value can be set using register sbv [2:0]. table 23. synchro bit value sbv[2:0] bit delay 000 0 chip_clk 001 1 chip_clk 010 2 chip_clk 011 3 chip_clk 100 4 chip_clk 101 5 chip_clk 110 6 chip_clk 111 7 chip_clk communication controller the communication controller block includes the arm cortex m0 32 bit risc processor, its peripherals: data ram, program rom, timers 1 and 2, interrupt control, test ? control, watchdog and power on reset (por), i/o ports and the serial communication interface (sci). the micro ? processor is programmed to handle the physical layer (chip synchronization), and the mac layer conform to iec 61334 ? 5 ? 1. the program is stored in a masked rom. the ram contains the necessary space to store the working data. the back ? end interface is done through the local port and serial communication interface block. this back ? end is used for data transmission with the application micro controller (containing the application layer for concentrator, power meter, or other functions) and for the definition of the modem configuration. more details can be found in reference 1.
NCN49597 http://onsemi.com 27 communication controller arm risc core por watchdog timer 1 & 2 interrupt control data ram resb test pc20091111.1 tx _enb tdi tdo tms trstb tck test control from receiver to transmit serial comm. interface local port rx _data txd rxd t _ req br 0 br 1 crc txd /pres program rom figure 24. communication controller reference in this document references are made to: 1. design manual NCN49597 http://www.onsemi.com 2. en 50065 ? 1: signaling on low ? voltage electrical installations in the frequency range 3 khz to 148.5 khz http://connect.nen.nl/~/preview.aspx?artfile=4257 28&rnr=66840 3. [3] erdf ? cpt ? linky ? spec ? fonc ? cpl version v1.0 linky plc profile functional specification http://www.erdfdistribution.fr/medias/linky/erd f ? cpt ? linky ? spec ? fonc ? cpl.pdf 4. dlms ua 1000 ? 2 ed. 7.0 dlms/cosem architecture and protocols http://www.dlms.com/documentation/dlmsuacolou redbookspasswordprotectedarea/index.html 5. iec 61334 ? 5 ? 1 lower layer s ? fsk profile. http://webstore.iec.ch/preview/info_iec61334 ? 5 ? 1 %7bed2.0%7db.pdf 6. iec 61334 ? 5 ? 1 lower layer s ? fsk profile. http://webstore.iec.ch/preview/info_iec61334 ? 5 ? 1 %7bed2.0%7db.pdf table 24. ordering information device temperature range package shipping ? NCN49597c5972g ? 25 c ? 80 c qfn ? 52 (pb ? free) tube NCN49597c5972rg ? 25 c ? 80 c qfn ? 52 (pb ? free) tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
NCN49597 http://onsemi.com 28 package dimensions case 485m ? 01 issue c c 0.15 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. a d e b c 0.08 a1 a3 a d2 l note 3 c 0.15 2x 2x seating plane c 0.10 a2 c e2 52 x e 1 13 14 26 27 39 40 52 b 52 x a 0.10 b c 0.05 c dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a2 0.60 0.80 a3 0.20 ref b 0.18 0.30 d 8.00 bsc d2 6.50 6.80 e 8.00 bsc e2 6.50 6.80 e 0.50 bsc k 0.20 --- ref k 52 x l 0.30 0.50 pin one reference soldering footprint dimensions: millimeters 8.30 6.75 6.75 0.50 0.62 0.30 52x 52x pitch 8.30 pkg outline recommended on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCN49597/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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